Dependence Analysis of VLIW Code for Non-Interlocked Pipelines

Data dependence analysis (DDA) on assembly code is a frequent problem in compilers and program analysis tools. The fundamentals of a DDA on code for simple processors are well understood. We propose a DDA method, that is applicable for a wider range of processors. This includes VLIW processors and processors with delayed branches and delayed register accesses. For these architectures, the instruction order may no longer match the order of register accesses, which necessitates a new analysis technique. The result of our analysis method is an instruction dependence graph (IDG), which also contains information on minimal instruction distances. For the mentioned architectures and allocated registers, the IDG may be cyclic. We discuss this phenomenon and outline an algorithm to reschedule such IDGs. We successfully implemented the DDA method and a respective scheduler in our compiler for the CoreVA VLIW architecture.